1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device suitable for forming wiring layers
2. Description of the Related Art
Via-first dual damascene for which an SiO group interlayer insulating film is used is adopted in recent microfabrication of wiring layers. In the dual damascene, occurrence of a fence between vias or a level difference in a via is restrained by controlling a height of an embedded material. When controlling the height thereof, the height of the embedded material corresponds to a height of one of the interlayer insulating film lying on a lower side.
Meanwhile, a low dielectric constant film is used as the interlayer insulating film between the wiring layers with an aim of lowering parasitic capacitance between the wiring layers or the like in order to enable high-speed operation.
A prior art is described in Japanese Patent Laid-open No. 2000-188329.
Also, when forming via-first dual damascene for which an SiOC group interlayer insulating film having low dielectric constant is used, occurrence of the fence between the vias or the level difference in the via needs to be restrained by controlling the height of the embedded material in the via.
Here, a problem when the height of the embedded material is inappropriately controlled according to a conventional manufacturing method is explained.
The problem when the height of the embedded material is too high is explained hereinafter. FIG. 6A to FIG. 6D are cross-sectional views showing a method for manufacturing a semiconductor device in order of processes when the height of the embedded material is too high.
As shown in FIG. 6A, on a wiring 101, an SiC film 102, an SiOC film 103, an SiC film 104, an SiOC film 105, a TEOS (Tetra Ethyl Ortho Silicate) film 106, and an SiN film 107 are first formed in this order. Then, a via hole 108 is formed in the SiN film 107, the TEOS film 106, the SiOC film 105, the SiC film 104, and the SiOC film 103. Thereafter, an embedded material 109 is embedded in the via hole 108. In this example, a surface of the embedded material 109 is between an upper surface of the SiOC film 105 and that of the Sic film 104. In other words, the embedded material 109 is higher than the SiOC film 105. After this, a resist mask 110 is formed by applying a resist on all surfaces and patterning it.
Next, as shown in FIG. 6B, the SiN film 107, the TEOS film 106, and the SiOC film 105 are etched by using the resist mask 110 as a mask until a surface of the SiC film 104 is exposed. As a result of this etching, a part of the SiOC film 105 remains on a side of the embedded material 109.
After this, as can be seen in FIG. 6C, the resist mask 110 and the embedded material 109 are removed by ashing.
Next, as shown in FIG. 6D, the SiC films 102 and 104 are removed by etching. At the same time, the SiN film 107, which has low etching selectivity against the SiC films 102 and 104, is removed. As a result of this etching, a trench 112 is formed, and the wiring 101 is exposed.
Thereafter, embedding of a wiring (not shown) or the like is carried out.
As described above, when the height of the embedded material 109 is too high according to the conventional manufacturing method, the part of the SiOC film 105 remaining on the side of the embedded material 109 during the process shown in FIG. 6B remains as it is in the trench 112, as shown in FIG. 6D.
The problem when the height of the embedded material is too low is explained hereinafter. FIG. 7A to FIG. 7D are cross-sectional views showing the method for manufacturing the semiconductor device in order of the processes when the height of the embedded material is too low.
First, as shown in FIG. 7A, the processes are carried out until the embedded material 109 is embedded in the via hole 108 in the same way as shown in FIG. 6A. However, in this example, the surface of the embedded material 109 is between an upper surface of the SiC film 102 and that of the SiOC film 103. In other words, the embedded material 109 is lower than the SiOC film 103. Then, the resist mask 110 is formed by applying the resist on all the surfaces and patterning it.
Then, as shown in FIG. 7B, the SiN film 107, the TEOS film 106, and the SiOC film 105 are etched by using the resist mask 110 as a mask until the surface of the SiC film 104 is exposed. In this example, the embedded material 109 is lower than the height at which the SiC film 104 is formed; therefore, an edge of the SiC film 104 is somewhat etched during this etching process. Consequently, a part of the SiOC film 103 covered by an etched part of the SiC film 104 is etched deeper than the upper surface of the embedded material 109. Accordingly, a level difference occurs on the SiOC film 103.
After this, as can be seen in FIG. 7C, the resist mask 110 and the embedded material 109 are removed by ashing.
Next, as shown in FIG. 7D, the SiC films 102 and 104 are removed by etching. At the same time, the SiN film 107, which has low etching selectivity against the SiC films 102 and 104, is removed. As a result of this etching, the trench 112 is formed, and the wiring 101 is exposed.
Thereafter, embedding of the wiring (not shown) or the like is carried out.
As described above, when the height of the embedded material 109 is too low according to the conventional manufacturing method, the level difference formed on the SiOC film 103 during the process shown in FIG. 7B remains as it is, as shown in FIG. 7D.
Therefore, as explained above, the height of the embedded material 109 needs to be strictly controlled.
However, the fence between the vias or the level difference in the via occur due to influence of resist poisoning or difficulty in controlling the height of the embedded material. These problems lead to decrease of process yield and reliability.